IntroductionQuantum Dot Cellular Automata also known as QCA is a moderntechnology that deals with computing of Integrated, Molecular and Nano scalecircuits. It provides improvement and fast development in respectiveperspective of scaling, designing complex structure and complex layout ofdifferent, diverse and advanced digital circuits. It also removes majordisadvantages that CMOS Technology possesses like maintaining low latency alongwith the high speed. It can be considered as one of the best alternative totypical CMOS technology in recent times.In Quantum Cellular Automata, all the operations are carriedout in a square form box also known as “Quantum Cell” or “QCA Cell”. ThisQuantum Cell consists of 4 or 5 dots that are known as “Quantum Dots” four ofthem present in the corner and one in the center.

Quantum dots is an areainside Quantum Cell where electrons can resides based on the chargeconfiguration. All the operations are carried out based on the placement ofthese electrons in the Quantum cell, Example – Polarization.Below presented figures shows two types of polarization thattake occurs based on the placement of electrons in the quantum cell.Here in Figure 1,Polarization P = +1 also known as “Logic 1” or “Binary 1”.Figure 1 -polarization 1Here in Figure 2,Polarization P = -1 also known as “Logic 0” or “Binary 0”.

If the Electrons are residingin all four corner of Quantum Cell means in all fours Quantum Dots then thatcan be considered as a new polarization where P = 0 often known as “NULL”.Figure 2 -polarization 2Design and Simulation Discussion In this report, we are exploring 3 different multiplexercircuits and trying to implement and analyze them with the perspective of theQuantum Cellular Automata logic. Here we are using tool called QCA DesignerVersion 2.0.

3 to design a complex structure like multiplexer by applying QCAlogic.2:1 Multiplexer This Figure showsdifferent components of 2:1 Multiplexer. There are two inputs having itsrespective value 1) I0 = -1.00 and 2) I1 = 1.00.

It also contains one selectorS and one output OUT. Selector selects input value path based on which theoutput is determined. So if selector S = 0, it takes path 1 and this willconnect I0 to OUT and if selector S = 1, it takes path 2 and this will connectI1 to OUT.

To sum it up we have following equation OUT =  I1+S.I0.Figure 4 -Simulation Result for 2:1 Multiplexer4:1 MultiplexerFigure 5 – 4:1Multiplexer by implying QCA LogicThis Figure shows different components of 4:1 Multiplexer.There are four inputs having its respective value 1) I0 = -1.00 2) I1 = 1.00 3)I2 = -1.00 and 4) I3 = 1.

00. It also contains two selectors S1 and S0 and oneoutput OUT. Selector selects input value path based on which the output isdetermined. So if the value of selector S1 S0=”00″, it takes path 1 and thiswill connect I0 to OUT, if the value of selector S1 S0=”01″, it takes path 2and this will connect I1 to OUT, if the value of selector S1 S0=”10″, it takespath 3 and this will connect I2 to OUT and if the value of selector S1 S0=”11″,it takes path 4 and this will connect I4 to OUT. To sum it up we have followingequation OUT =) I0 + .S0) I1 + ) I2 + (S1.

S0) I3.Figure 6 -Simulation Result of 4:1 Multiplexer8:1 MultiplexerFigure 7 – 8:1Multiplexer by implying QCA Logic This Figure shows different componentsof 8:1 Multiplexer. There are Eight inputs having its respective value 1) I0 =-1.00 2) I1 = 1.00 3) I2 = -1.

00 4) I3 = 1.00 5) I4 = -1.00 6) I5 = 1.00 7) I6= -1.00 8) I7 = 1.00.

It also contains three selectors S0, S1 and S2 and oneoutput OUT. Selector selects input value path based on which the output is determined.So if the value of selector S2 S1 S0=”000″, it takes path 1 and this willconnect I0 to OUT, if the value of selector S2 S1 S0=”001″, it takes path 2 andthis will connect I1 to OUT, if the value of selector S2 S1 S0=”010″, it takespath 3 and this will connect I2 to OUT, if the value of selector S2 S1S0=”011″, it takes path 4 and this will connect I3 to OUT, if the value ofselector S2 S1 S0=”100″, it takes path 5 and this will connect I4 to OUT, ifthe value of selector S2 S1 S0=”101″, it takes path 6 and this will connect I5to OUT, if the value of selector S2 S1 S0=”110″, it takes path 7 and this willconnect I6 to OUT and if the value of selector S2 S1 S0=”111″, it takes path 8and this will connect I7 to OUT.

To sum it up we have following equation OUT =) I0 + .S0) I1 + ) I2 + .S1.S0) I3 + .S2) I4+ .

S0.S2) I5 + ) I6 + (S1.S2.S0) I7.Figure 8 -Simulation Result of 8:1 MultiplexerNow let’s analyze what the above mention simulation resultsfor each multiplexer has to offer as an advantages.

The Table shown belowdescribes each and every impacted and affected parameter that comes in playwhile simulating all the multiplexer. So let’s talk about Cell Count first, 2:1Multiplexer utilizes total 12 Quantum cells in about 0.01um area which isreally less and impressive as well for designing its circuit and implying QCAlogic while 4:1 Multiplexer utilizes total 61 Quantum cells in about 0.08umarea so if we compare here 2:1 and 4:1 Multiplexer circuit here there’s anincrease in cell count tremendously but area has not changed radically andthat’s a good sign because covering 61 cells in only 0.08um is progressive whencomes to designing its circuit and 8:1 Multiplexer utilizes total 175 Quantumcells in just about 0.24um area so now let’s compare 4:1 and 8:1 Multiplexercircuit here the cell count has approximately tripled and same goes for the areait takes 175 cells to get ready for working operation and for designing itscircuit. Structure Cell Count Area Latency Cross Wiring 2:1 MUX 12 0.

01 1 No 4:1 MUX 61 0.08 4 Coplanar 8:1 MUX 175 0.24 6 Coplanar  Now let’s compare the latency means the delay that takeplace for the data to be transfer and starts following operating instruction.Delay of one clock cycle takes place for 2:1 Multiplexer that’s not badconsidering it as an advanced and complex structured circuit while Delay offour clock cycle takes place for 4:1 Multiplexer here the clock cycle increaseswhich is not a good sign this can be considered as an disadvantage of this 4:1Multiplexer circuit, But while moving forward we see that there’s a Delay of sixclock cycle for 8:1 Multiplexer circuit which is pretty impressive consideringthe above mentioned fact that cell and the area both the parameter got tripledbut during this process the clock cycle decreases for 8:1 Multiplexer circuit.By comparing each all the above mentioned circuit with eachother we can say that as we progress on the path of 2n:1 with eachprogression there’s any improvement in cell count, area and latency. Thus 8:1Multiplexer here provide us more reliable and efficient output and bettersimulation result that the other two. One more advantage that 8:1 Multiplexerhave is that it has coplanar cross wiring , the same can be considered as anadvantage for 4:1 Multiplexer as well while there’s no cross wiring takingplace for 2:1 Multiplexer.ConclusionIn these report, we have explored 3 different Multiplexerand their architecture i.

e. 2:1 Multiplexer, 4:1 Multiplexer and 8:1Multiplexer and concluded that each of them utilizes different and advanced characteristicsof quantum technology to produce the desired output. We have a simulated theresult for each of the above mentioned Multiplexer using tool called QCADesigner.

The conclusion table depicted above provides us an understandingabout the improvement in cell count, latency, area and power consumptioncompared to the previous QCA multiplexer structures and other technology suchas CMOS.References1.      Optimizedmultiplexer design and simulation using quantum dot-cellular automata byJadav Chandra Dasa  & Debashis Deb – http://op.niscair.res.

in/index.php/IJPAP/article/viewFile/6108/9942.      Optimized Design of Multiplexor byQuantum-dot Cellular Automata by M. Kianpour* , R. Sabbaghi-Nadooshan – http://www.ijnnonline.

net/article_3875_d489f58478dba026ccf478554344b89c.pdf     IntroductionQuantum Dot Cellular Automata also known as QCA is a moderntechnology that deals with computing of Integrated, Molecular and Nano scalecircuits. It provides improvement and fast development in respectiveperspective of scaling, designing complex structure and complex layout ofdifferent, diverse and advanced digital circuits. It also removes majordisadvantages that CMOS Technology possesses like maintaining low latency alongwith the high speed. It can be considered as one of the best alternative totypical CMOS technology in recent times.In Quantum Cellular Automata, all the operations are carriedout in a square form box also known as “Quantum Cell” or “QCA Cell”. ThisQuantum Cell consists of 4 or 5 dots that are known as “Quantum Dots” four ofthem present in the corner and one in the center.

Quantum dots is an areainside Quantum Cell where electrons can resides based on the chargeconfiguration. All the operations are carried out based on the placement ofthese electrons in the Quantum cell, Example – Polarization.Below presented figures shows two types of polarization thattake occurs based on the placement of electrons in the quantum cell.Here in Figure 1,Polarization P = +1 also known as “Logic 1” or “Binary 1”.Figure 1 -polarization 1Here in Figure 2,Polarization P = -1 also known as “Logic 0” or “Binary 0”.If the Electrons are residingin all four corner of Quantum Cell means in all fours Quantum Dots then thatcan be considered as a new polarization where P = 0 often known as “NULL”.Figure 2 -polarization 2Design and Simulation Discussion In this report, we are exploring 3 different multiplexercircuits and trying to implement and analyze them with the perspective of theQuantum Cellular Automata logic.

Here we are using tool called QCA DesignerVersion 2.0.3 to design a complex structure like multiplexer by applying QCAlogic.2:1 Multiplexer This Figure showsdifferent components of 2:1 Multiplexer. There are two inputs having itsrespective value 1) I0 = -1.00 and 2) I1 = 1.

00. It also contains one selectorS and one output OUT. Selector selects input value path based on which theoutput is determined. So if selector S = 0, it takes path 1 and this willconnect I0 to OUT and if selector S = 1, it takes path 2 and this will connectI1 to OUT. To sum it up we have following equation OUT =  I1+S.I0.Figure 4 -Simulation Result for 2:1 Multiplexer4:1 MultiplexerFigure 5 – 4:1Multiplexer by implying QCA LogicThis Figure shows different components of 4:1 Multiplexer.There are four inputs having its respective value 1) I0 = -1.

00 2) I1 = 1.00 3)I2 = -1.00 and 4) I3 = 1.00. It also contains two selectors S1 and S0 and oneoutput OUT. Selector selects input value path based on which the output isdetermined. So if the value of selector S1 S0=”00″, it takes path 1 and thiswill connect I0 to OUT, if the value of selector S1 S0=”01″, it takes path 2and this will connect I1 to OUT, if the value of selector S1 S0=”10″, it takespath 3 and this will connect I2 to OUT and if the value of selector S1 S0=”11″,it takes path 4 and this will connect I4 to OUT.

To sum it up we have followingequation OUT =) I0 + .S0) I1 + ) I2 + (S1.S0) I3.Figure 6 -Simulation Result of 4:1 Multiplexer8:1 MultiplexerFigure 7 – 8:1Multiplexer by implying QCA Logic This Figure shows different componentsof 8:1 Multiplexer. There are Eight inputs having its respective value 1) I0 =-1.00 2) I1 = 1.

00 3) I2 = -1.00 4) I3 = 1.00 5) I4 = -1.00 6) I5 = 1.00 7) I6= -1.

00 8) I7 = 1.00. It also contains three selectors S0, S1 and S2 and oneoutput OUT.

Selector selects input value path based on which the output is determined.So if the value of selector S2 S1 S0=”000″, it takes path 1 and this willconnect I0 to OUT, if the value of selector S2 S1 S0=”001″, it takes path 2 andthis will connect I1 to OUT, if the value of selector S2 S1 S0=”010″, it takespath 3 and this will connect I2 to OUT, if the value of selector S2 S1S0=”011″, it takes path 4 and this will connect I3 to OUT, if the value ofselector S2 S1 S0=”100″, it takes path 5 and this will connect I4 to OUT, ifthe value of selector S2 S1 S0=”101″, it takes path 6 and this will connect I5to OUT, if the value of selector S2 S1 S0=”110″, it takes path 7 and this willconnect I6 to OUT and if the value of selector S2 S1 S0=”111″, it takes path 8and this will connect I7 to OUT. To sum it up we have following equation OUT =) I0 + .S0) I1 + ) I2 + .S1.S0) I3 + .S2) I4+ .S0.

S2) I5 + ) I6 + (S1.S2.S0) I7.Figure 8 -Simulation Result of 8:1 MultiplexerNow let’s analyze what the above mention simulation resultsfor each multiplexer has to offer as an advantages. The Table shown belowdescribes each and every impacted and affected parameter that comes in playwhile simulating all the multiplexer.

So let’s talk about Cell Count first, 2:1Multiplexer utilizes total 12 Quantum cells in about 0.01um area which isreally less and impressive as well for designing its circuit and implying QCAlogic while 4:1 Multiplexer utilizes total 61 Quantum cells in about 0.08umarea so if we compare here 2:1 and 4:1 Multiplexer circuit here there’s anincrease in cell count tremendously but area has not changed radically andthat’s a good sign because covering 61 cells in only 0.08um is progressive whencomes to designing its circuit and 8:1 Multiplexer utilizes total 175 Quantumcells in just about 0.24um area so now let’s compare 4:1 and 8:1 Multiplexercircuit here the cell count has approximately tripled and same goes for the areait takes 175 cells to get ready for working operation and for designing itscircuit. Structure Cell Count Area Latency Cross Wiring 2:1 MUX 12 0.01 1 No 4:1 MUX 61 0.08 4 Coplanar 8:1 MUX 175 0.

24 6 Coplanar  Now let’s compare the latency means the delay that takeplace for the data to be transfer and starts following operating instruction.Delay of one clock cycle takes place for 2:1 Multiplexer that’s not badconsidering it as an advanced and complex structured circuit while Delay offour clock cycle takes place for 4:1 Multiplexer here the clock cycle increaseswhich is not a good sign this can be considered as an disadvantage of this 4:1Multiplexer circuit, But while moving forward we see that there’s a Delay of sixclock cycle for 8:1 Multiplexer circuit which is pretty impressive consideringthe above mentioned fact that cell and the area both the parameter got tripledbut during this process the clock cycle decreases for 8:1 Multiplexer circuit.By comparing each all the above mentioned circuit with eachother we can say that as we progress on the path of 2n:1 with eachprogression there’s any improvement in cell count, area and latency. Thus 8:1Multiplexer here provide us more reliable and efficient output and bettersimulation result that the other two. One more advantage that 8:1 Multiplexerhave is that it has coplanar cross wiring , the same can be considered as anadvantage for 4:1 Multiplexer as well while there’s no cross wiring takingplace for 2:1 Multiplexer.ConclusionIn these report, we have explored 3 different Multiplexerand their architecture i.

e. 2:1 Multiplexer, 4:1 Multiplexer and 8:1Multiplexer and concluded that each of them utilizes different and advanced characteristicsof quantum technology to produce the desired output. We have a simulated theresult for each of the above mentioned Multiplexer using tool called QCADesigner. The conclusion table depicted above provides us an understandingabout the improvement in cell count, latency, area and power consumptioncompared to the previous QCA multiplexer structures and other technology suchas CMOS.References1.

Optimizedmultiplexer design and simulation using quantum dot-cellular automata byJadav Chandra Dasa  & Debashis Deb – http://op.niscair.res.in/index.php/IJPAP/article/viewFile/6108/9942.      Optimized Design of Multiplexor byQuantum-dot Cellular Automata by M.

Kianpour* , R. Sabbaghi-Nadooshan – http://www.ijnnonline.net/article_3875_d489f58478dba026ccf478554344b89c.pdf

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