ABSTRACT–Power consumption plays a majorrole in present day VLSI design technology. The demand for low power consumingdevices is increasing rapidly and the adiabatic logic is becoming a greatsolution. This paper presents animplementation of adiabatic logic in CMOS with comprehensive analysis andevaluation of static adiabatic logic circuitswhere the current flow through the circuit is controlled such that the energydissipation due to switching and capacitor dissipation is minimized. The staticadiabatic logic has an advantage in the form of reduction in switching energywhile comparing with the dynamic adiabatic logic. This advantage is realizeddue to the fact that the discharging operation at a node happens only when theinput signal transition demands a change in the state of the output. Keywords—Adiabatic logic,low power, CMOS, power consumption, dynamic adiabatic logic. I.
INTRODUCTION In recent years,the demand for battery operated portable products, hand held devices andwireless communication systems have grown significantly 1. This requires theVLSI designers to have low power consumption as an important parameter to beconsidered while designing digital integrated circuits. Adiabatic switching isone of the promising approaches among the various non-conventional low powerdesign methodologies. They work based on the principle of energy recovery fromthe circuit nodes, rather than allowing the charge to dissipate from the nodeto ground.
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The energy recovery circuits are broadly classified into fullyadiabatic and quasi adiabatic circuits. Former has asymptotically zero energyconsumption with complex circuit structure 2. On the other hand, the quasiadiabatic circuits are less complex and incur both adiabatic and non -adiabaticlosses. The structure and operational complexity, such as 1) the number ofoperating power-clock phases, 2) single/dual rail outputs, 3) realization of charging/discharging path and 4) reversible and irreversible of logic styles differ fromone other 3. Most of the energy recovery circuits 4-7 in the literatureare dynamic in nature i.e.
the output node charges and discharges for everyclock cycle irrespective of the input signal. Hence, they suffer from thedrawbacks of 1) higher switching activity in output nodes, 2) multiphase andmultiple clock generation and clock signal distributions across the circuit and3) the existence of differential signaling that adds to the signal overhead.Adiabatic logicis an implementation of reversible logic in CMOS where the current flow throughthe circuit is controlled such that the energy dissipation due to switching andcapacitor dissipation is minimized 4. This is accomplished by recyclingcircuit energy rather than dissipating it into the surrounding environment.This is beneficial for CMOS implementations, since the input and output chargesare kept separate, with the objective of reduction of leakage power and leakagecurrent. Adiabatic logic implementations of CMOS have been used to improvepower consumption in comparison to pass transistor logic 5. Adiabatic logicrequires the use of ramp functions instead of the faster switching achieved instep functions.
The main contributions of the circuit can be listed as follows: 1)the high on-chip voltage achieved from a 1.2 V supply; 2) the digitallyprogrammable output voltage; 3) the design for a small area, such that it isamenable to tight integration with MEMS; 4) the fast rise and fall times in themicroseconds range to allow for sufficiently fast actuation (i.e.
, MEMStypically operate in the sub millisecond or millisecond range); 5) the improvedpower consumption through the use of a variable frequency clock; and 6) theintegrated discharge stage immune to breakdown at the output for fast dischargeof the MEMS capacitive load. This paper is organized as follows. Section II provides thegeneral concept of CMOS logic, Section III describes about adiabatic logic,SectionIV describes the techniques under this logic,Section V provides a conclusion. II. CMOS LOGIC Power dissipationin conventional CMOS circuits primarilyoccurs during device switching. When thelogic level in the system is “1,” there is a sudden flow of current through channelresistanceR. Q = CLVdd is the charge supplied by the positive power supply railfor charging CL to Vdd. CL is the node capacitance , which is referred to asthe load capacitance.
Hence, the energy drawn from the power supply is Q.Vdd =CLV2dd 6. If it is assumed that the energy drawn from powersupply is equal tothat supplied to CL, the energy stored in CLbecomes one half the suppliedenergy, i.
e. Estored=(½) CLVdd2 theremaining energy is dissipated in R. The same amount of energy is dissipatedduring discharging in the NMOS network when the logic level in the system is”0.” Therefore, the total amount of energy dissipated as heat during chargingand discharging is given by: E charge + E discharge= CL Vdd2 From the aboveequation, it is apparent that the energy consumption in a conventional CMOScircuit can be reduced by scaling Vdd and/or CL down. By decreasing theswitching frequency in the circuit, the power consumption(P=dE/dT) gets suppressed proportionally 7.
Here, the loadcapacitance (CL) is charged by a constant current source (I). ConventionalLogic Switching In conventionalCMOS level-restoring logic which uses the constant voltage source Vdd, theswitching event of circuits with rail-to-rail output voltage swing causes anenergy transfer from the power supply to the output node or from the outputnode to the ground. Fig.1.
Conventional CMOS Chargingand DischargingDuring a 0-to-VDDtransition of the output, the total output charge Q= CL VDD is drawnfrom the power supply at a constant voltage. Thus, energy E = CL VDD2isdrawn from the power supply during this transition. Charging the output nodecapacitance to the voltage level VDD means that at the end of the transition,the amount of stored energy in the output node is E = ½ CL VDD2.Thus,half of the injected energy from the power supply is dissipated in the PMOSnetwork while only one half is delivered to the output node 3. During asubsequent VDD-to-0 transition of the output node, no charge is drawn from thepower supply and the energy stored in the load capacitance is dissipated in theNMOS network. To reduce the dissipation, the circuit designer can minimize theswitching events, decrease the node capacitance, reduce the voltage swing, orapply a combination of these methods. III. DESCRIPTION OF ADIABATIC LOGIC Principle ofAdiabatic Logic Implementation ofthe adiabatic logic on a circuit reduces the power by reusing the stored energyfrom thecircuit nodes.
Thus, the term adiabatic logic is used in low-power VLSIcircuits, where the energy recovery from the circuit nodes is made possible.The power clock plays an important role in the adiabatic circuits. Each phaseof the power clock guides the operation of each stage of the adiabatic circuit.The basic characteristics of the adiabatic circuits which realize no or verylittle power dissipation are the following: 1) Never turn on thetransistor when there is a voltage across its drain and source (VDS >0), 2) The second rule is to never turn off a transistor device, if thereis a current flowing through it at any point of time (IDS _ 0) and 3)Never pass the current through a diode which form part of the adiabatic logic.The adiabatic circuits reclaim the energy during their recovery phase, i.e.,when the nodes are discharging from their charged state.
Hence, this logichelps to reduce the overall power and energy dissipation of the circuits.Inclusion of such an adiabatic logic in the memory cell design will saveconsiderable amount of power in the high density systems. Several adiabaticlogic circuits powered by trapezoidal power clocks have been presented in theliterature2.
The widely used power clocks exhibit four different phases, namedas evaluate, hold, recover and wait or idle phase. Switching characteristics The powerconsumption of the electronic devices can be reduced by adopting differentdesign styles. Adiabatic computation has been widely studied as a low – powerdesign technique. To increase the energy efficiency of the logic circuits, thecircuit topology and the operating principles have to be modified as per theneed arises. The amount of energy recycling 1 achievable using adiabatictechniques is also determined by the process technology, switching speed, andthe voltage swing. This circuit can be modified to recover signal energy byutilizing ramped power-clock signals instead of static operating voltage andground. Constant currentsource is used,i(t)=c dV/dt =cVdd/T (1) Energy duringchargingE=( I2*R)*Tramp(2) The voltageacross the switch = I*RQ=CL*Vdd ,I = (CL*Vdd)/Tramp Eadiabatic=(I2*R)*Tramp (3)Therefore Eadiabatic=R*C2 * Vdd2/Tramp Where,E – Energy dissipated duringcharging timeQ – Charge transferred to the loadCL – the value of the loadcapacitanceR – on resistance of the PMOSswitchVdd – the final value of thevoltage at the loadTramp – is thecharging time IV.
TECHNIQUES IN ADIABATICLOGIC a. LOGIC STRUCTURESAdiabatic logicstructures are mainly of two types: 1. Partially adiabatic logic, which isclassified as Efficient charge recovery logic (ECRL), Quasi AdiabaticLogic(QAL) , Positive feedback adiabatic logic (PFAL), NMOS energy recoverylogic, True single phase adiabatic logic (TSAL) 2. Fully adiabatic logic, Classified asPass transistor adiabatic logic, 2 Phase adiabatic Static CMOS logic (2PASCL),Split rail charge recovery logic (SCRL) 1.
1. ECRLThe logicfunction in efficient charge recovery logic structure is estimated by pairs ofpull down devices(NMOS) alsothrough PMOS device, ECRL is not able to pick up the power clock which performslike quasi adiabatic logic style. ECRL implements a technique of performingsimultaneous pre-charge and evaluation. FIG1.1 ECRLINVERTER· Logic function in ECRL inverter is, when powerclock goes up starting from zero to VDD, output stays in ground level and whenpower clock reaches at VDD, outputs ‘out’ and ‘/out’ hold logic value zero andVDD respectively. This output values will be used for the next stage.· Whenpower clock falls from VDD to zero, ‘/out’ returns its energy to power clockwhich recovers the delivered charge.
1.2. PFALThe logic leveldegradation is avoided in positive feedback adiabatic logic by latch which wascreated with help of two PMOS and two NMOS devices. Similar to ECRL, the logicfunction in PFAL is determined by NMOS devices but connected parallely withPMOS devices. Advantages of PFAL is transmission gate formation, positive andnegative ouput generated through the functional blocks. FIG1.
2PFAL INVERTER· Logicfunction in PFAL is, when power clock goes up from zero to VDD, output (out)stays at ground level and /out follows power clock. When power clock arrives atVDD, out and /out hold logic value zero and VDD. This output values can be usedfor the next stage.· When power clock falls from VDD to zero, /outreturns its energy to power clock which recovers delivered charge.
1.3. SCRLA conventional,stastic, logic structure does not need dual rail input. It is possible to buildasymptotically zero power CMOS using this technique and ‘Split-Level ChargeRecovery Logic'(SCRL) based inverter is shown in below circuit .Two phasepower-clock supplies are implemented here, where power clock, input and ouputvoltage are at a voltage of VDD/2 when inverter is in idle condition. FIG1.3SCRL INVERTERb.
STATIC ADIABATIC LOGIC FAMILIESA. Inverter Circuits The invertercircuits for QSERL, CEPAL, ASL and QSECRL in figThe comparison of all thestatic adiabatic circuits in terms of number of clock per phase, number oftransistors used and the floating node output is listed in Table I. The staticadiabatic circuits are powered by sinusoidal power clock signal.
Power clock(PC) consists of evaluate and hold phase. During the evaluate phase, the newoutput is computed and it charges or discharges. The energy is supplied to thecircuit and recovered back by the PC and PCBAR.
During hold phase, the outputremains the same. The input is allowed to change during hold phase and it hasto be maintained constant during evaluate phase. B. Quasi-inverter circuitsQuasi inverter isa partially adiabatic logic inverter in which shown below circuit has pulsedpower clock supply instead of DC supply like CMOS inverter shown first. Comparewith conventional logic this adiabatic logic inverter gives reduced powerdissipation of 6.37E-20w. V. CONCLUSIONInthis paper,it has been observed that, Adiabatic CMOS circuits can be successfully used toimplement a digital circuit design using gradually rising and fallingpower-clock.
The static adiabatic circuits prove to hold advantage over theirdynamic counterparts, namely, the quasi-adiabatic circuits found in theliterature, in terms of their reduced switching. The adiabatic circuit designcan be improved by introducing conventional power supply. Further to improveswitching speed of adiabatic circuit as compare to CMOS logic new adiabaticcircuits with better switching speed can be designed. VI. REFERENCES 1. MinakshiSanadhya1,M.Vinoth Kumar2,SRM University – NCR Campus,”Recent Development inEfficient Adiabatic Logic Circuits and Power Analysis with CMOS Logic”.Modinagar, Ghaziabad.
2. P.Sasipriya1,V.S.Kanchana Bhaaskaran2VIT University, “Two Phase Sinusoidal Power ClockedQuasi-Static Adiabatic Logic Families”. School of Electrical Engineering VITUniversity, Chennai, India.
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