8086 MicroprocessorIntroduction:Microprocessor is an integrated circuit that contains all the functions of a CPU. It is made by fabricating millions of transistors on a single chip. Journey of microprocessors started with a 4bit microprocessor named as 4004; and was made by Intel Corporation in 1971. With the development of the microprocessors they came up with a 16bit microprocessor named as 8086 in 1978 and with the release of 8086, starts the journey of personal computing.

8086 Microprocessor:Elements of 8086 microprocessor architecture:? 16bit internal data bus? 20bit address bus: 220 = 1,048,576 = 1 megabyte? Control bus? Execution unit? Bus interface unitAmong the on-chip peripherals are: ? 2 direct memory access controllers (DMA) ? Three 16-bit programmable timers ? Clock generator ? Chip select unit ? Programmable Control Registers8086 processor model:The 8086 processor model is divided into two units:? Bus Interface Unit (BIU)? Execution Unit (EU)Bus Interface Unit (BIU): The BIU provides hardware functions, including generation of the memory and I/0 addresses for the transfer of data between itself and the outside world.  Following functions are supported by BIU:? It provides a full 16 bit bidirectional data bus and 20 bit address bus. ? It sends address of memory or I/O. ? It fetches instruction from memory. ? It reads data from port/memory. ? It writes data into port/memory.

 ? It supports instruction queuing . ? It makes 8086’s interface to the outside world. ? The BIU uses a mechanism known as an instruction stream queue to implement a pipeline architecture.

 ? If the BIU is already in the process of fetching an instruction when the EU request it to read or write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle before initiating the operand read / write cycle. ? The BIU also contains a dedicated adder which is used to generate the 20bit physical address. Execution Unit (EU):The EU receives program instruction codes and data from the BIU, executes these instructions, and stores the results in the general registers.

Following functions are supported by BIU:? The Execution unit is responsible for decoding and executing all instructions. ? The EU extracts instructions from the top of the queue in the BIU. ? During the execution of the instruction, the EU tests the status and control flags and updates them based on the results of executing the instruction. ? If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top of the queue. ? The EU accesses the queue from the output end. It reads one instruction byte after the other from the output of the queue. ? It tells BIU from where to fetch instructions or data, decodes instructions & execute instructions.The main linkage between the two functional blocks is the instruction queue, with the BIU looking ahead of the current instruction being executed in order to keep the queue filled with instructions for the EU to decode and operate on.

 Instruction Queue:? It is of 6 Bytes. ? To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time from memory. ? It operates on the principle first in first out (FIFO). ? Then all bytes are given to EU one by one. ? This pre-fetching operation of BIU may be in parallel with execution operation of EU. ? It improves the execution speed of the instruction. The Fetch and Execute Cycle The organization of the processor into a separate BIU and EU allows the fetch and execute cycles to overlap.

To see this, consider what happens when the 8086 is first started. ? The BIU outputs the contents of the instruction pointer register (IP) onto the address bus, causing the selected byte or word in memory to be read into the BIU. ? Register IP is incremented by one to prepare for the next instruction fetch.

 ? Once inside the BIU, the instruction is passed to the queue: a first-in/first-out storage register sometimes likened to a pipeline. ? Assuming that the queue is initially empty, the EU immediately draws this instruction from the queue and begins execution. ? While the EU is executing this instruction, the BIU proceeds to fetch a new instruction.

? Depending on the execution time of the first instruction, the BIU may fill the queue with several new instructions before the EU is ready to draw its next instruction. ? The cycle continues, with the BIU filling the queue with instructions and the EU fetching and executing these instructions. The BIU is programmed to fetch a new instruction whenever the queue has room for two additional bytes. The advantage to this pipelined architecture is that the EU can execute instructions (almost) continually instead of having to wait for the BIU to fetch a new instruction. This is shown schematically in the following Figure


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